1. Technical Field of the Invention
The present invention relates to a power electronic device integrated on a semiconductor substrate and relative manufacturing process.
The present invention particularly, but not exclusively, relates to a power MOSFET device of the multi-drain type, and the following description is made with reference to this field of application for convenience of illustration only.
2. Description of Related Art
As is well known, power MOS devices with a breakdown voltage between 200 and 1000V have a high “on” resistance due mainly to the epitaxial drain layer resistance which is necessary to sustain high voltages. This high “on” resistance further depends on the dopant concentration of the epitaxial layer itself.
However, it is possible to obtain power MOS devices with a low “on” resistance and a high breakdown voltage BV by modifying the epitaxial layer concentration.
A known device of the MOS type which meets this need is shown in FIG. 1. Such a power MOS device 3 of the multi-drain type comprises a highly doped semiconductor substrate 1 of the N+ type, whereon a semiconductor epitaxial layer 2 is formed of the same N type.
The epitaxial layer 2 forms a common drain layer for a plurality of elemental units which form the power MOS device 3. Each elemental unit comprises a body region 4 of the P type realized on the epitaxial layer 2.
In the epitaxial layer 2, below each body region 4, a column region 5 of the P type is present extending downwards for the whole thickness of the epitaxial layer 2 towards the semiconductor substrate 1.
In particular, each column region 5 is aligned and in contact with respective body region 4.
In this power MOS device 3 of the known type, as shown in FIG. 2 wherein the concentration of the epitaxial layer 2 is shown as function of its thickness, the epitaxial layer 2 of the N type has a constant resistivity. Also the column regions 5 have a constant concentration along the whole development of the column as shown in FIG. 3 wherein the concentration of the column regions 5 is shown as a function of their thickness.
The power MOS device 3 also has, inside the body regions 4, highly doped source regions 6 of the N type.
The surface of the epitaxial layer 2 is thus covered with a thin gate oxide layer 7 and with a polysilicon layer 8. Openings are thus provided in the polysilicon layer 8 and in the thin gate oxide layer 7 to expose the surface of the epitaxial layer 2 in correspondence with each source region 6. An insulating layer 9 covers completely the polysilicon layer 8 and partially the source regions 6, so as to allow a source metallic layer 10 to contact the source regions 6 and the body regions 4. A drain metallic layer 10A is also provided on the semiconductor substrate 1 lower surface 1.
Thus, the presence of the column regions 5 allows to reduce the resistivity of the epitaxial layer 2 without decreasing the breakdown voltage BV of the device 3. With this kind of device 3 it is thus possible to reach a predetermined voltage BV which has a resistivity of the epitaxial layer 2 lower than that necessary with conventional devices.
Although advantageous is several respects, this device has some drawbacks.
In fact, as shown in FIG. 4A, the breakdown voltage BV varies when the concentration of the dopant of the P type in the epitaxial drain layer increases: in particular, the voltage BV is highest when the dopant concentration of the epitaxial drain layer is completely balanced by an implant dose ΦE used to realize the column regions 5. In other words, the introduced dopant in the column regions has to over compensate for the dopant in the epitaxial drain layer in order to form a P region from N layer and this over compensation is performed so that the number of dopant atoms of P type (that exceed the compensation) are equal to the number of dopant atoms of N type of the external region to the column 5. This condition is indicated as “charge balance”.
If the implant dose Φ used to realize the column regions 5 is lower than the implant dose ΦE, the concentration of the column regions 5 is lower than the concentration of the column regions 5 obtained in the case of “charge balance”. This condition is indicated as “P charge defect” or, in the same way, “N charge excess”. If instead the implant dose Φ used to realize the column regions 5 is higher than the implant dose ΦE, the concentration of the column regions 5 is higher than the concentration of the column regions 5 used in the case of “charge balance”. This condition is indicated as “P charge excess” or, in the same way, “N charge defect”.
As it has been said, under both these conditions the breakdown voltage BV of the obtained devices is lower than that which is obtained by using the implant dose ΦE.
However, as shown in FIG. 4B, when the concentration of the dopant of the P type in the column regions 5 increases, the avalanche current value IUIS decreases, i.e., the maximum current the device 3 can switch in an unclamped switch.
For this reason, currently used devices are realized so as to sustain a voltage BV lower than the maximum one which can be obtained, so that an avalanche current IUIS can be available being higher than the one which can be obtained when, in the epitaxial drain layer, there is charge balance, i.e., between the dopant concentration of the P type and of the N type.
Tests carried out by the Applicant have highlighted that the decrease of the avalanche current value IUIS when the concentration of the P dopant in the column regions 5 increases is caused by the increase of the electric field on the bottom of the column regions 5.
In particular, such increase of the value of the electric field on the bottom of the column regions 5 is evident from the diagrams of FIG. 4C, wherein the curve A shows the trend of the electric field value inside the column regions 5 under “P charge excess” conditions, the curve B shows the trend of the electric field value inside the column regions 5 under “charge balance” condition, whereas the curve C shows the trend of the electric field value inside the column regions 5 under “N charge excess” conditions.
The technical problem underlying the present invention is that of forming a multi-drain device which, under charge balance conditions, has the highest breakdown voltage BV, thus overcoming the limits still affecting the devices realized according to the prior art. Advantageously, the value of the electric field on the bottom of the column regions is remarkably reduced so as to simultaneously maximize the avalanche current.